ARM architecture forms the basis for every ARM processor. Over time, the ARM architecture has evolved to include architectural features to meet the growing demand for new functionality, high performance and the needs of new and emerging markets. For information on the latest announced version, see ARMv8 Architecture.
The ARM architecture supports implementations across a wide range of performance points, establishing it as the leading architecture in many market segments. The ARM architecture supports a very broad range of performance points leading to very small implementations of ARM processors, and very efficient implementations of advanced designs using state of the art micro-architecture techniques. Implementation size, performance, and low power consumption are key attributes of the ARM architecture.
ARM developed architecture extensions to provide support for Java acceleration (Jazelle®), security (TrustZone®), SIMD, and Advanced SIMD (NEON™) technologies. The ARMv8-architecture adds a Cryptographic extension as an optional feature.
The ARM architecture is similar to a Reduced Instruction Set Computer (RISC) architecture, as it incorporates these typical RISC architecture features:
A uniform register file load/store architecture, where data processing operates only on register contents, not directly on memory contents.
Simple addressing modes, with all load/store addresses determined from register contents and instruction fields only.
Enhancements to a basic RISC architecture enable ARM processors to achieve a good balance of high performance, small code size, low power consumption and small silicon area.
A32 (ARM)
T32 (Thumb)
ARM, generically known as A32, is a fixed-length (32-bit) instruction set. It is the base 32-bit ISA used in the ARMv4T, ARMv5TEJ and ARMv6 architectures. In these architectures it is used in applications requiring high performance, or for handling hardware exceptions such as interrupts and processor start-up.
The ARM ISA is also supported in the Cortex™-A and Cortex-R profiles of the Cortex architecture for performance critical applications, and for legacy code. Most of its functionality is subsumed into the Thumb instruction set with the introduction of Thumb-2 technology. Thumb (T32) benefits from improved code density.
ARM instructions are 32-bits wide, and are aligned on 4-byte boundaries.
Most ARM instructions can be “conditionalised” to only execute when previous instructions have set a particular condition code. This means that instructions only have their normal effect on the programmers’ model operation, memory and coprocessors if the N, Z, C and V flags in the Application Program Status Register satisfy a condition specified in the instruction. If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next instruction as normal, including any relevant checks for exceptions being taken, but has no other effect. This conditionalisation of instructions allows small sections of if- and while-statements to be encoded without the use of branch instructions.
The condition codes are:
Condition Code Meaning
N
Negative condition code, set to 1 if result is negative
Z
Zero condition code, set to 1 if the result of the instruction is 0
C
Carry condition code, set to 1 if the instruction results in a carry condition
V
Overflow condition code, set to 1 if the instruction results in an overflow condition.
ARM architecture forms the basis for every ARM processor. Over time, the ARM architecture has evolved to include architectural features to meet the growing demand for new functionality, high performance and the needs of new and emerging markets. For information on the latest announced version, see ARMv8 Architecture.
The ARM architecture supports implementations across a wide range of performance points, establishing it as the leading architecture in many market segments. The ARM architecture supports a very broad range of performance points leading to very small implementations of ARM processors, and very efficient implementations of advanced designs using state of the art micro-architecture techniques. Implementation size, performance, and low power consumption are key attributes of the ARM architecture.
ARM developed architecture extensions to provide support for Java acceleration (Jazelle®), security (TrustZone®), SIMD, and Advanced SIMD (NEON™) technologies. The ARMv8-architecture adds a Cryptographic extension as an optional feature.
The ARM architecture is similar to a Reduced Instruction Set Computer (RISC) architecture, as it incorporates these typical RISC architecture features:
A uniform register file load/store architecture, where data processing operates only on register contents, not directly on memory contents.
Simple addressing modes, with all load/store addresses determined from register contents and instruction fields only.
Enhancements to a basic RISC architecture enable ARM processors to achieve a good balance of high performance, small code size, low power consumption and small silicon area.
A32 (ARM)
T32 (Thumb)
ARM, generically known as A32, is a fixed-length (32-bit) instruction set. It is the base 32-bit ISA used in the ARMv4T, ARMv5TEJ and ARMv6 architectures. In these architectures it is used in applications requiring high performance, or for handling hardware exceptions such as interrupts and processor start-up.
The ARM ISA is also supported in the Cortex™-A and Cortex-R profiles of the Cortex architecture for performance critical applications, and for legacy code. Most of its functionality is subsumed into the Thumb instruction set with the introduction of Thumb-2 technology. Thumb (T32) benefits from improved code density.
ARM instructions are 32-bits wide, and are aligned on 4-byte boundaries.
Most ARM instructions can be “conditionalised” to only execute when previous instructions have set a particular condition code. This means that instructions only have their normal effect on the programmers’ model operation, memory and coprocessors if the N, Z, C and V flags in the Application Program Status Register satisfy a condition specified in the instruction. If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next instruction as normal, including any relevant checks for exceptions being taken, but has no other effect. This conditionalisation of instructions allows small sections of if- and while-statements to be encoded without the use of branch instructions.
The condition codes are:
Condition Code Meaning
N
Negative condition code, set to 1 if result is negative
Z
Zero condition code, set to 1 if the result of the instruction is 0
C
Carry condition code, set to 1 if the instruction results in a carry condition
V
Overflow condition code, set to 1 if the instruction results in an overflow condition.